1. Field of the Invention
The present invention is related to power management, and more particularly, to a power management circuit using a voltage regulator to control the substrate bias and supply voltage in a CMOS digital circuitry.
2. Description of the Prior Art
With the advances in complementary metal oxide semiconductor (CMOS) technology, the channel length and the diffusion area of a transistor are decreased, which has an advantage of low parasitic capacitance effect in a CMOS circuitry. However, when the diffusion area of the transistor is reduced, the short channel effect will occur. It will increase the leakage current of the transistor to further cause larger power consumption in an integrated circuit. In order to overcome such problem, body biasing apparatus is designed. The body biasing apparatus in the CMOS circuit is capable of decreasing the junction capacitance between the diffusion region and substrate.
Please refer to FIG. 1. FIG. 1 is diagram illustrating a conventional body biasing apparatus 10. The conventional body biasing apparatus 10 utilizes a charge pump 14a, 14b to generate a positive voltage V+ that is higher than a system voltage (Vdd), and to generate a negative voltage V− that is lower than a ground voltage (Vgnd), respectively control the body of the PMOS transistor MP and the body of the NMOS transistor MN of CMOS circuit 12. In normal operation, switching control signal SB_enable controls switches 16a, 16b to selectively connect to the system voltage Vdd and the ground voltage Vss. In other words, the body of the PMOS transistor MP and the body of the NMOS transistor MN are respectively connected to the system voltage Vdd and the ground voltage Vss. Please note that, when the source of the PMOS transistor MP and the source of the NMOS transistor MN are respectively connected to the system voltage Vdd and the ground voltage Vss, the body of the PMOS transistor MP and the body of the NMOS transistor MN are also connected to the system voltage Vdd and the ground voltage Vss, respectively. Alternatively, when system operates in standby mode, switching control signal SB_enable controls switch 16a to choose voltage V+, then the substrate of the PMOS transistor MP is connected to a voltage that is higher than the system voltage Vdd. Accordingly, the threshold voltage of PMOS transistor MP is thereby increased that will reduce the leakage current because the substrate voltage is higher than the source voltage. Similarly, in the standby mode, switching control signal SB_enable controls switch 16b to choose voltage V− to thereby increase the threshold voltage of NMOS transistor MN that will also reduce the leakage current.
However, the operation of charge pumps 14a, 14b is driven by an oscillator that provides the clock signal to control the charging and the discharging of the capacitor, therefore an extra consume current is required by the conventional body biasing apparatus 10 that will increase the number of devices on the chip. Furthermore, if the voltage V+, V− is provided by, for example, an off chip source, then not all of the voltage can be supplied from off chip, thereby some of the pins of the chip will be needed for adding the receiving voltage V+, V−.